`timescale 1ns / 1ps
module my_adder(
    input clk, 
    input rst, 
    input logic[0:0] ready,
    input logic [7:0] in_a,
    input logic [7:0] in_b,
    output logic [7:0] out,
    output logic [0:0] valid
    );
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            out <= 8'b0;
            valid <= 0;
        end else if (ready) begin
            out <= in_a + in_b;
            valid <= 1;
        end else begin
            out <= out;
            valid <= 0;
        end
    end
endmodule
